Status information of a semiconductor memory device includes device identification (DI) information, revision identification (RI) information, refresh rate (RR) information, device width (DW) information, device type (DT) information and density (DS) information. The DI information is fixed information as information for identifying a manufacturer, and the RI information is variable information as information for defining a revision performance version. The RR information is variable information as information on refresh performance timing, and the DW information is variable information as information for defining the number of data bits outputted in accordance with an address input. The DT information is fixed information as information on capacity of the semiconductor memory device, and the DS information is fixed information on an integration degree of the semiconductor memory device.
Such status information of a semiconductor memory device is stored in a register. A user can identify the status information of the semiconductor memory device stored in the register through status register read (SRR).
The SRR is specified in JEDEC SPEC as follows: i) The SRR is started after a power-up period is ended. ii) A read command for the SRR is inputted in an idle state after application of MRS. iii) BL is fixed to 2 during SRR operation. iv) tSRR=2 CLK, tSRC=CL+1. v) The SRR is ended when a bank active command is inputted. An operation timing diagram of the SRR specified in the JEDEC SPEC is shown with reference to FIG. 1.
In the JEDEC SPEC specified as described above, the conditions ii) and v) will be more specifically described. Before the read command for the SRR is inputted, the semiconductor memory device should be in an idle state. Therefore, when the bank active command is inputted before the read command for the SRR is inputted, the SRR is not normally performed but ended.
Since a general read operation of a semiconductor memory device is performed after bank activation, there have been increased requests for SRR which is, like the read operation, not ended but can be normally performed even though a read command for SRR is inputted after the bank active command for the bank active is inputted. However, in a semiconductor memory device according to the JEDEC SPEC, such requests cannot be satisfied.